-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "05/06/2025 16:48:59"

-- 
-- Device: Altera EP3C40F780C8 Package FBGA780
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	lab2 IS
    PORT (
	clk : IN std_logic;
	rst : IN std_logic;
	key_row : IN std_logic_vector(3 DOWNTO 0);
	key_col : BUFFER std_logic_vector(3 DOWNTO 0);
	seg : BUFFER std_logic_vector(7 DOWNTO 0)
	);
END lab2;

-- Design Ports Information
-- key_col[0]	=>  Location: PIN_AD11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_col[1]	=>  Location: PIN_AD12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_col[2]	=>  Location: PIN_AF13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_col[3]	=>  Location: PIN_AE14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[0]	=>  Location: PIN_G16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[1]	=>  Location: PIN_G17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[2]	=>  Location: PIN_F18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[3]	=>  Location: PIN_G18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[4]	=>  Location: PIN_G15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[5]	=>  Location: PIN_G14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[6]	=>  Location: PIN_G12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[7]	=>  Location: PIN_M21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- clk	=>  Location: PIN_A14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- rst	=>  Location: PIN_Y27,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_row[3]	=>  Location: PIN_AE11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_row[1]	=>  Location: PIN_AE12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_row[2]	=>  Location: PIN_AF11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- key_row[0]	=>  Location: PIN_AE13,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF lab2 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_key_row : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_key_col : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_seg : std_logic_vector(7 DOWNTO 0);
SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \rst~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \key_col[0]~output_o\ : std_logic;
SIGNAL \key_col[1]~output_o\ : std_logic;
SIGNAL \key_col[2]~output_o\ : std_logic;
SIGNAL \key_col[3]~output_o\ : std_logic;
SIGNAL \seg[0]~output_o\ : std_logic;
SIGNAL \seg[1]~output_o\ : std_logic;
SIGNAL \seg[2]~output_o\ : std_logic;
SIGNAL \seg[3]~output_o\ : std_logic;
SIGNAL \seg[4]~output_o\ : std_logic;
SIGNAL \seg[5]~output_o\ : std_logic;
SIGNAL \seg[6]~output_o\ : std_logic;
SIGNAL \seg[7]~output_o\ : std_logic;
SIGNAL \clk~input_o\ : std_logic;
SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
SIGNAL \cnt[0]~1_combout\ : std_logic;
SIGNAL \rst~input_o\ : std_logic;
SIGNAL \rst~inputclkctrl_outclk\ : std_logic;
SIGNAL \cnt[1]~0_combout\ : std_logic;
SIGNAL \Decoder0~0_combout\ : std_logic;
SIGNAL \Decoder0~1_combout\ : std_logic;
SIGNAL \Decoder0~2_combout\ : std_logic;
SIGNAL \Decoder0~3_combout\ : std_logic;
SIGNAL \key_row[2]~input_o\ : std_logic;
SIGNAL \key_row[1]~input_o\ : std_logic;
SIGNAL \seg[0]~0_combout\ : std_logic;
SIGNAL \key_row[3]~input_o\ : std_logic;
SIGNAL \Selector6~0_combout\ : std_logic;
SIGNAL \key_row[0]~input_o\ : std_logic;
SIGNAL \seg[0]~1_combout\ : std_logic;
SIGNAL \seg[0]~reg0_q\ : std_logic;
SIGNAL \Selector5~4_combout\ : std_logic;
SIGNAL \Selector5~5_combout\ : std_logic;
SIGNAL \Selector5~6_combout\ : std_logic;
SIGNAL \seg[1]~reg0_q\ : std_logic;
SIGNAL \Selector4~2_combout\ : std_logic;
SIGNAL \Selector4~3_combout\ : std_logic;
SIGNAL \seg[2]~reg0_q\ : std_logic;
SIGNAL \Selector3~2_combout\ : std_logic;
SIGNAL \Selector3~3_combout\ : std_logic;
SIGNAL \seg[3]~reg0_q\ : std_logic;
SIGNAL \Selector2~0_combout\ : std_logic;
SIGNAL \Selector2~1_combout\ : std_logic;
SIGNAL \seg[4]~reg0_q\ : std_logic;
SIGNAL \Selector1~0_combout\ : std_logic;
SIGNAL \Selector1~1_combout\ : std_logic;
SIGNAL \seg[5]~reg0_q\ : std_logic;
SIGNAL \Selector5~7_combout\ : std_logic;
SIGNAL \Selector0~0_combout\ : std_logic;
SIGNAL \Selector0~1_combout\ : std_logic;
SIGNAL \seg[6]~reg0_q\ : std_logic;
SIGNAL cnt : std_logic_vector(1 DOWNTO 0);
SIGNAL \ALT_INV_Decoder0~2_combout\ : std_logic;
SIGNAL \ALT_INV_Decoder0~1_combout\ : std_logic;
SIGNAL \ALT_INV_Decoder0~0_combout\ : std_logic;

BEGIN

ww_clk <= clk;
ww_rst <= rst;
ww_key_row <= key_row;
key_col <= ww_key_col;
seg <= ww_seg;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);

\rst~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \rst~input_o\);
\ALT_INV_Decoder0~2_combout\ <= NOT \Decoder0~2_combout\;
\ALT_INV_Decoder0~1_combout\ <= NOT \Decoder0~1_combout\;
\ALT_INV_Decoder0~0_combout\ <= NOT \Decoder0~0_combout\;

-- Location: IOOBUF_X1_Y0_N23
\key_col[0]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Decoder0~0_combout\,
	devoe => ww_devoe,
	o => \key_col[0]~output_o\);

-- Location: IOOBUF_X1_Y0_N9
\key_col[1]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Decoder0~1_combout\,
	devoe => ww_devoe,
	o => \key_col[1]~output_o\);

-- Location: IOOBUF_X27_Y0_N16
\key_col[2]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_Decoder0~2_combout\,
	devoe => ww_devoe,
	o => \key_col[2]~output_o\);

-- Location: IOOBUF_X34_Y0_N9
\key_col[3]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \Decoder0~3_combout\,
	devoe => ww_devoe,
	o => \key_col[3]~output_o\);

-- Location: IOOBUF_X43_Y43_N30
\seg[0]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[0]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[0]~output_o\);

-- Location: IOOBUF_X50_Y43_N23
\seg[1]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[1]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[1]~output_o\);

-- Location: IOOBUF_X54_Y43_N16
\seg[2]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[2]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[2]~output_o\);

-- Location: IOOBUF_X48_Y43_N16
\seg[3]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[3]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[3]~output_o\);

-- Location: IOOBUF_X41_Y43_N9
\seg[4]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[4]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[4]~output_o\);

-- Location: IOOBUF_X29_Y43_N23
\seg[5]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[5]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[5]~output_o\);

-- Location: IOOBUF_X11_Y43_N16
\seg[6]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[6]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[6]~output_o\);

-- Location: IOOBUF_X67_Y35_N2
\seg[7]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \seg[7]~output_o\);

-- Location: IOIBUF_X34_Y43_N15
\clk~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_clk,
	o => \clk~input_o\);

-- Location: CLKCTRL_G14
\clk~inputclkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \clk~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~inputclkctrl_outclk\);

-- Location: LCCOMB_X29_Y1_N2
\cnt[0]~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \cnt[0]~1_combout\ = !cnt(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => cnt(0),
	combout => \cnt[0]~1_combout\);

-- Location: IOIBUF_X67_Y22_N15
\rst~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_rst,
	o => \rst~input_o\);

-- Location: CLKCTRL_G9
\rst~inputclkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \rst~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \rst~inputclkctrl_outclk\);

-- Location: FF_X29_Y1_N3
\cnt[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \cnt[0]~1_combout\,
	clrn => \rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => cnt(0));

-- Location: LCCOMB_X29_Y1_N4
\cnt[1]~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \cnt[1]~0_combout\ = cnt(0) $ (cnt(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt(0),
	datac => cnt(1),
	combout => \cnt[1]~0_combout\);

-- Location: FF_X29_Y1_N5
\cnt[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \cnt[1]~0_combout\,
	clrn => \rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => cnt(1));

-- Location: LCCOMB_X29_Y1_N24
\Decoder0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Decoder0~0_combout\ = (cnt(0) & cnt(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt(0),
	datac => cnt(1),
	combout => \Decoder0~0_combout\);

-- Location: LCCOMB_X29_Y1_N22
\Decoder0~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Decoder0~1_combout\ = (!cnt(0) & cnt(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt(0),
	datac => cnt(1),
	combout => \Decoder0~1_combout\);

-- Location: LCCOMB_X29_Y1_N28
\Decoder0~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Decoder0~2_combout\ = (cnt(0) & !cnt(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => cnt(0),
	datac => cnt(1),
	combout => \Decoder0~2_combout\);

-- Location: LCCOMB_X29_Y1_N18
\Decoder0~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Decoder0~3_combout\ = (cnt(0)) # (cnt(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => cnt(0),
	datad => cnt(1),
	combout => \Decoder0~3_combout\);

-- Location: IOIBUF_X27_Y0_N1
\key_row[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_key_row(2),
	o => \key_row[2]~input_o\);

-- Location: IOIBUF_X29_Y0_N15
\key_row[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_key_row(1),
	o => \key_row[1]~input_o\);

-- Location: LCCOMB_X30_Y1_N28
\seg[0]~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \seg[0]~0_combout\ = (\key_row[2]~input_o\ & \key_row[1]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \key_row[2]~input_o\,
	datad => \key_row[1]~input_o\,
	combout => \seg[0]~0_combout\);

-- Location: IOIBUF_X29_Y0_N8
\key_row[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_key_row(3),
	o => \key_row[3]~input_o\);

-- Location: LCCOMB_X30_Y1_N20
\Selector6~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector6~0_combout\ = (\key_row[3]~input_o\ & (((!\seg[0]~0_combout\)) # (!cnt(0)))) # (!\key_row[3]~input_o\ & (((cnt(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111011111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => cnt(0),
	datab => \seg[0]~0_combout\,
	datac => cnt(1),
	datad => \key_row[3]~input_o\,
	combout => \Selector6~0_combout\);

-- Location: IOIBUF_X32_Y0_N1
\key_row[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_key_row(0),
	o => \key_row[0]~input_o\);

-- Location: LCCOMB_X30_Y1_N18
\seg[0]~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \seg[0]~1_combout\ = (\key_row[3]~input_o\ & ((\key_row[0]~input_o\ & (\key_row[2]~input_o\ $ (\key_row[1]~input_o\))) # (!\key_row[0]~input_o\ & (\key_row[2]~input_o\ & \key_row[1]~input_o\)))) # (!\key_row[3]~input_o\ & (\key_row[0]~input_o\ & 
-- (\key_row[2]~input_o\ & \key_row[1]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110100010000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_row[3]~input_o\,
	datab => \key_row[0]~input_o\,
	datac => \key_row[2]~input_o\,
	datad => \key_row[1]~input_o\,
	combout => \seg[0]~1_combout\);

-- Location: FF_X30_Y1_N21
\seg[0]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector6~0_combout\,
	clrn => \rst~inputclkctrl_outclk\,
	ena => \seg[0]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[0]~reg0_q\);

-- Location: LCCOMB_X29_Y1_N14
\Selector5~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector5~4_combout\ = (cnt(1) & !cnt(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => cnt(1),
	datad => cnt(0),
	combout => \Selector5~4_combout\);

-- Location: LCCOMB_X30_Y1_N12
\Selector5~5\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector5~5_combout\ = (\key_row[3]~input_o\ & ((\key_row[1]~input_o\ $ (\Selector5~4_combout\)) # (!\key_row[2]~input_o\))) # (!\key_row[3]~input_o\ & (((\Selector5~4_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111111110001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_row[1]~input_o\,
	datab => \key_row[3]~input_o\,
	datac => \key_row[2]~input_o\,
	datad => \Selector5~4_combout\,
	combout => \Selector5~5_combout\);

-- Location: LCCOMB_X30_Y1_N22
\Selector5~6\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector5~6_combout\ = (cnt(1) & (((\Selector5~5_combout\)))) # (!cnt(1) & (((!cnt(0))) # (!\key_row[3]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101111100010011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_row[3]~input_o\,
	datab => cnt(1),
	datac => cnt(0),
	datad => \Selector5~5_combout\,
	combout => \Selector5~6_combout\);

-- Location: FF_X30_Y1_N23
\seg[1]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector5~6_combout\,
	clrn => \rst~inputclkctrl_outclk\,
	ena => \seg[0]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[1]~reg0_q\);

-- Location: LCCOMB_X30_Y1_N14
\Selector4~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector4~2_combout\ = (\key_row[3]~input_o\ & !\key_row[2]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_row[3]~input_o\,
	datac => \key_row[2]~input_o\,
	combout => \Selector4~2_combout\);

-- Location: LCCOMB_X30_Y1_N24
\Selector4~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector4~3_combout\ = (cnt(1) & (((\Selector5~5_combout\)))) # (!cnt(1) & (((cnt(0))) # (!\Selector4~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110100110001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Selector4~2_combout\,
	datab => cnt(1),
	datac => cnt(0),
	datad => \Selector5~5_combout\,
	combout => \Selector4~3_combout\);

-- Location: FF_X30_Y1_N25
\seg[2]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector4~3_combout\,
	clrn => \rst~inputclkctrl_outclk\,
	ena => \seg[0]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[2]~reg0_q\);

-- Location: LCCOMB_X29_Y1_N20
\Selector3~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector3~2_combout\ = (\key_row[2]~input_o\ & (\key_row[1]~input_o\ $ (cnt(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \key_row[1]~input_o\,
	datac => cnt(0),
	datad => \key_row[2]~input_o\,
	combout => \Selector3~2_combout\);

-- Location: LCCOMB_X29_Y1_N16
\Selector3~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector3~3_combout\ = (\key_row[3]~input_o\ & ((cnt(1) $ (cnt(0))) # (!\Selector3~2_combout\))) # (!\key_row[3]~input_o\ & (cnt(1) & (cnt(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110100011101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_row[3]~input_o\,
	datab => cnt(1),
	datac => cnt(0),
	datad => \Selector3~2_combout\,
	combout => \Selector3~3_combout\);

-- Location: FF_X29_Y1_N17
\seg[3]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector3~3_combout\,
	clrn => \rst~inputclkctrl_outclk\,
	ena => \seg[0]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[3]~reg0_q\);

-- Location: LCCOMB_X30_Y1_N16
\Selector2~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector2~0_combout\ = (\key_row[2]~input_o\ & ((cnt(0)) # (!\key_row[1]~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_row[1]~input_o\,
	datac => \key_row[2]~input_o\,
	datad => cnt(0),
	combout => \Selector2~0_combout\);

-- Location: LCCOMB_X30_Y1_N26
\Selector2~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector2~1_combout\ = (cnt(0) & ((cnt(1)) # ((\key_row[3]~input_o\ & \Selector2~0_combout\)))) # (!cnt(0) & (\key_row[3]~input_o\ & ((!\Selector2~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110000011001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_row[3]~input_o\,
	datab => cnt(1),
	datac => cnt(0),
	datad => \Selector2~0_combout\,
	combout => \Selector2~1_combout\);

-- Location: FF_X30_Y1_N27
\seg[4]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector2~1_combout\,
	clrn => \rst~inputclkctrl_outclk\,
	ena => \seg[0]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[4]~reg0_q\);

-- Location: LCCOMB_X29_Y1_N6
\Selector1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector1~0_combout\ = (\key_row[3]~input_o\ & (((\key_row[1]~input_o\ & \key_row[2]~input_o\)) # (!cnt(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000101000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_row[3]~input_o\,
	datab => \key_row[1]~input_o\,
	datac => cnt(0),
	datad => \key_row[2]~input_o\,
	combout => \Selector1~0_combout\);

-- Location: LCCOMB_X29_Y1_N26
\Selector1~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector1~1_combout\ = (cnt(1) & ((cnt(0) $ (\Selector1~0_combout\)))) # (!cnt(1) & ((cnt(0)) # ((\seg[0]~0_combout\ & \Selector1~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011111011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \seg[0]~0_combout\,
	datab => cnt(1),
	datac => cnt(0),
	datad => \Selector1~0_combout\,
	combout => \Selector1~1_combout\);

-- Location: FF_X29_Y1_N27
\seg[5]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector1~1_combout\,
	clrn => \rst~inputclkctrl_outclk\,
	ena => \seg[0]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[5]~reg0_q\);

-- Location: LCCOMB_X29_Y1_N30
\Selector5~7\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector5~7_combout\ = (\key_row[3]~input_o\ & (!\seg[0]~0_combout\ & (!cnt(0) & cnt(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_row[3]~input_o\,
	datab => \seg[0]~0_combout\,
	datac => cnt(0),
	datad => cnt(1),
	combout => \Selector5~7_combout\);

-- Location: LCCOMB_X29_Y1_N8
\Selector0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector0~0_combout\ = ((cnt(0) & ((\key_row[2]~input_o\) # (!\key_row[3]~input_o\)))) # (!cnt(1))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \key_row[3]~input_o\,
	datab => \key_row[2]~input_o\,
	datac => cnt(0),
	datad => cnt(1),
	combout => \Selector0~0_combout\);

-- Location: LCCOMB_X29_Y1_N12
\Selector0~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Selector0~1_combout\ = (\Selector5~7_combout\ & ((\key_row[3]~input_o\) # ((\Decoder0~3_combout\)))) # (!\Selector5~7_combout\ & (\Selector0~0_combout\ & ((\key_row[3]~input_o\) # (\Decoder0~3_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101011001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Selector5~7_combout\,
	datab => \key_row[3]~input_o\,
	datac => \Selector0~0_combout\,
	datad => \Decoder0~3_combout\,
	combout => \Selector0~1_combout\);

-- Location: FF_X29_Y1_N13
\seg[6]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Selector0~1_combout\,
	clrn => \rst~inputclkctrl_outclk\,
	ena => \seg[0]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[6]~reg0_q\);

ww_key_col(0) <= \key_col[0]~output_o\;

ww_key_col(1) <= \key_col[1]~output_o\;

ww_key_col(2) <= \key_col[2]~output_o\;

ww_key_col(3) <= \key_col[3]~output_o\;

ww_seg(0) <= \seg[0]~output_o\;

ww_seg(1) <= \seg[1]~output_o\;

ww_seg(2) <= \seg[2]~output_o\;

ww_seg(3) <= \seg[3]~output_o\;

ww_seg(4) <= \seg[4]~output_o\;

ww_seg(5) <= \seg[5]~output_o\;

ww_seg(6) <= \seg[6]~output_o\;

ww_seg(7) <= \seg[7]~output_o\;
END structure;


